1. Field of the Invention
The invention relates in general to the field of computer aided electronic circuit design tools and in particular to a computer based method for providing manufacturing test simulation in the circuit design process to enable improved design for test and design for manufacturability earlier in the circuit design process.
2. Description of related art
Electronic products of today are designed under tremendous internal and external pressures. Competitive market pressure relating to time to market dictates new product announcements every one to two years and a particular product may be viable for only six months to one year. Rapidly increasing performance capability of circuits adds to the pressures on circuit designers to complete a design before new technology obsoletes a product design.
Modern circuit designs are rapidly increasing in complexity. In addition, several factors contribute to a demand for smaller electronic product size. In addition to market concerns for reducing product size, the performance of modern electronic circuits is frequently impacted by the size of the circuit. Signal propagation delays can render modern high speed circuits non-functional. The technology of circuit board assembly is evolving to support density demands of many modern circuit designs. Multi-chip modules (MCMs) and twelve-mil pitch surface mount technology (SMT) are frequently used to improve circuit density. SMT chip packages with lead counts of over 1000 are not uncommon. New fabrication processes which are used to enable higher circuit densities usually have higher defect rates than older low density fabrication technologies. Faster circuits are less tolerant of delay faults, resulting in the increase in the component functional defect rate. Higher defect rates imply lower yields and higher costs in manufacturing.
Another trend in the electronics industry is the focus on quality control and quality improvement at all stages of a product's life cycle. To achieve such quality control and defect reduction, there is an emphasis on design for test (DFT), design for quality (DFQ), and design for manufacturing (DFM) in the early design of electronic circuits. However, time and cost factors tend to make such design efforts difficult to justify in a short term, profit oriented, perspective. In order to maximize short term profits, a company needs to justify a return on investment of all features implemented in a product. Testability features, such as the IEEE 1149.1 boundary scan standard, are no exception since they require significant hardware investment which needs to be justified (See "IEEE 1149.1: How to Justify Implementation," Proceedings of the 1993 International Test Conference, 265, October 1993).
Often, such DFT/DFQ/DFM features are ignored during the early design phases of a circuit to minimize the time in design. Such features are sometimes added later in the design as a designer begins to consider manufacturing issues relating to the product. An example of this practice is DFM violations in board layout. For example, designers would like to minimize the area of surface mount pads to increase board density and minimize interconnect parasitic. However, SMT design rules require minimum pad geometries, and violation of these rules will result in increased solder defects in manufacturing. Another example is the placement of test pads on a board for in-circuit test access. Designers will usually wait until the board is completely routed before placing test pads. At that late stage in the design, the board is often too dense to allow the addition of desirable test points. The result is the reduction of test coverage for in-circuit board test. The solder defects not covered by in-circuit test will typically be detected later at the functional test step, with an increased cost for defect isolation and repair.
Many electronic products (especially computing products) are designed to meet high performance specifications dictated by the marketplace. The design engineer's first priority is to get a product to market within the narrow time-to-market window, and to meet the product price/performance specifications. DFM and DFT aspects of the product frequently are relegated to secondary concerns. DFM and DFT activity is usually performed by consulting with the manufacturing expert at selected times in the design cycle. This consultation is usually in the form of design reviews or enforcement of guidelines. There is a limited understanding of the trade-offs available in board manufacturing because, designers and manufacturing experts have different goals for the product. In this environment, the added manufacturing costs caused by poor quality and inefficient test process are not visible to the designer due to the lack of reliable design specific data. The result is that the DFT and DFM of the product suffers, and the product is not optimized for manufacturability and testability.
A fundamental problem exists in that design tools used by circuit designers are focused on functionality and tend to neglect manufacturing and testability issues. Designers are not accustomed to addressing manufacturability issues in their design processes. To effectively address manufacturability issues during design is frequently called Concurrent Engineering. Concurrent Engineering is defined as the product development paradigm where, the manufacturing aspects of the product are developed concurrently with the functional design of the product. However, in order to practice concurrent engineering successfully, designers need tools to help them understand manufacturing issues and trade-offs.
Typical prior approaches to measuring and testing for manufacturing include the stuck-at fault coverage metric and its failure rate estimations, automatic test pattern generation, scan methodologies, and built-in self test (BIST) methodologies (see T. W. Williams & K. P. Parker, "Design For Testability--A Survey," Proceedings of the IEEE, Vol. 71, 98-112, January 1983). Several DFT and test development techniques have evolved, and have been bench-marked against the stuck-at coverage metric. The major concern in board manufacturing has been the integrated circuit (IC) defect level, that is, what is the probability of a defect in an IC after it undergoes all of its IC level testing (See T. W. Williams & N. C. Brown, "Defect level as a function of fault coverage," IEEE Transactions on Computers, Vol. C-30, No. 12, 987-988, December 1981). IC defect level is important to board manufacturing but does not fully evaluate design quality from the overall perspective of manufacturing. In addition, ICs and systems are merging, requiring quality assurance methods more robust than what stuck-at model based fault simulation can provide. In computer products faults arise in a system, involving delay faults, chip to chip interactions, an ever changing fault spectrum (not characterized by defect density), and faults that need to be efficiently isolated to the defect and be repaired.
Work at Hewlett-Packard's Colorado Computer Manufacturing Operation (see M. V. Tegethoff et al., "Board Test DFT Model for Computer Products," Proceedings of the 1992 International Test Conference, 367-71), demonstrated that modeling aspects of the test process is quite effective in fostering DFT techniques. However, the HP work only covered the cost and quality aspects of the product assuming that critical manufacturing attributes, such as defect rates and test coverage, were otherwise known. In addition, all calculations were performed based on categories, making some of the statistical assumptions questionable, since the defect levels can become large on a parts per million basis. The yield modeling of the HP work was based on binomial statistics which is clearly insufficient in dealing with complex SMT. Finally, the spreadsheet model used in the HP work did not allow for more than two test steps and it was targeted to be used by expert manufacturing test engineers rather than circuit designers.
The prior approaches in board manufacturing can be broken into five categories (discussed below), board level report card tools, board level economic models, DFM tools, semiconductor tools, and test equipment analysis.